There are generally three types of ICs that a circuit designer may use to implement a custom design.
A field-programmable gate array (FPGA) is an integrated circuit having a number of circuit blocks that can be interconnected in any desired manner by programming interconnection switches disposed on the FPGA die. Therefore, a circuit designer may program the FPGA with firmware to implement any circuit that the FPGA is capable of implementing.
A full-custom application-specific integrated circuit (ASIC) is laid out on the transistor level to implement the designer's circuit. Typically, the designer presents a circuit topology, in the form of a netlist, to a semiconductor manufacturer. The manufacturer lays out the circuit (typically with placing and routing software) transistor by transistor.
A semi-custom ASIC is laid out on a circuit-cell level to implement the designer's circuit. Typically, the designer presents a circuit topology, in the form of a netlist, to the semiconductor manufacturer. The manufacturer lays out the circuit (typically with placing and routing software) cell by cell. Each cell contains a pre-established set of circuit components that may be interconnected as desired. For example, each cell may contain a flip-flop or another logic gate (for example, NAND gate, OR gate, inverter gate, etc.). The placing and routing software “builds” the circuit defined by the netlist using these cells, and then generates the appropriate node connections between the cells. The software may also define circuit macros, which are groups of cells interconnected in a pre-established manner. For example, the software may define a phase-locked loop (PLL) using the cells, so that the designer may designate a pre-established PLL in his netlist, instead of having to manually define the PLL on a cell-by-cell or a transistor-by-transistor basis.
FIG. 1 is a top view of a 9-cell portion 10 of a semi-custom ASIC. As an example, a semi-custom ASIC may include 100,000 or more cells 12 that are arranged in a checkerboard pattern. Typically, the higher the number of cells, the larger the IC die needed to implement the circuit.
FIG. 2 is a perspective view of a single cell 12 of FIG. 1.
The cell 12 includes a top conductive layer 14, which may be used, for example, as a portion of a power-supply plane VDD. That is, because the cells are contiguous in the ASIC, the top layer 14 of each cell merges with the top layers 14 of the contiguous cells to form a continuous conductive plane that spans the entire die.
Beneath the top layer 14 is an insulator layer 16 and another conductive layer 18, which may be used, for example, as a portion of a ground plane.
A region 20 includes one or more polysilicon and/or metal interconnection layers that form, for example, interconnections between the components within the cell 12 and also connections from the cell to neighboring cells. This region may also include layers that form, for example, polysilicon structures such as transistor gates.
A substrate 22 may be made from silicon, another semiconductor material, or another appropriate material, and may include, for example, the drain and source regions of CMOS transistors, the base, emitter, and collector regions of bipolar transistors, and isolation structures such as isolation trenches or field-oxide regions.
The cell 12 may include other layers and regions that are not shown in FIG. 2.
Still referring to FIG. 2, the region 20 and the substrate 18 of the cell 12 contain a predetermined arrangement of components therein. For example, the cell 12 may include transistors that are connected together to form, for example, a flip-flop, one or more combinatorial logic gates (for example, a NAND gate, a NOR gate, an inverter), or some combination of the same. The interconnections between these intracellular components as specified by the designer may be implemented in the one or more metal layers within the region 20. Alternatively, the interconnections between these intracellular components may be fixed, and the designer may later on specify the interconnections between cells.
So the design process for a semi-custom IC is typically as follows.
The designer provides a circuit netlist in some hardware description language, for example, Verilog, which defines the functionality of the circuit.
Next, the manufacturer takes this netlist and using known techniques (for example, Synthesis) determines how many cells will be needed to implement the circuit, and thus the minimum dimensions of the die that are needed to implement the circuit.
The manufacturer includes in this estimate of the number of cells, a number of additional cells, often called “spare” cells. These spare cells are available at a later stage of manufacturing or after the manufacturing of the die to correct problems that are found during various testing stages of the die. For example, it may be discovered that a signal that needs to be inverted at a certain point is not inverted. Therefore, the manufacturer may use an inverter in a spare cell to invert this signal. If the mistake is in the layout itself, then the manufacturer may merely change the mask of an appropriate one of the metal layers in the region 20 to make this connection to the spare inverter, such that all subsequently manufactured versions of the circuit work properly. Alternatively, if the problem is limited to one or a small number of ASICs, then the manufacture may use ion-beam or other similar technologies to manually route the signal through the spare inverter. Using spare cells in this manner may significantly increase the yield of the semi-custom ASIC, and thus significantly reduce the cost per ASIC.
As an example, assume that a circuit design requires 100,000 cells for implementation. Using known techniques, the manufacturer may determine that for such a circuit, statistically speaking, 10% or 10,000 additional spare cells are needed to make sure that there are enough spare cells to correct any defects that may occur post layout and manufacture of the chip.
After the number of needed cells is determined (the sum of the cells needed for the circuit implementation plus the statistically determined number of spare cells, for a total of 110,000 in this example), the manufacturer generates a modified netlist that adds the spare cells to the circuit cells. For example, the manufacturer may add spare macro circuits to the netlist, each macro circuit including a variety of spare cells. For example, assume that there are sequential and combinatorial logic gate cells. The manufacturer wants spares of all these different types of cells located throughout the chip. So the manufacturer may generate these macros including at least one of each of these types of cells. For example, the manufacturer may create a macro that is a ring oscillator including all these types of components, with the intent that the ring oscillator not be used as a ring oscillator but for its components if spares are needed.
Typically, even a very efficient utilization of IC area means that an implemented circuit, including the spare cells, does not utilize 100% of the chip area. Therefore, even in designs that use the IC area efficiently, around 40% of the area can still be unused.
Now if this unused area were left empty, that is, void of cells, then there would be “holes” in the IC as one looks down from above where no functional or spare cells are needed.
To plug these holes, filler cells are used.
Referring to FIG. 2, a filler cell is similar to the cell 12 except that it typically includes no interconnections for netlist functionality within the region 20. That is, the region 20 may just include continuous layers, or a continuous single layer such as an insulator layer or some rudimentary maintenance constructs. However, the conductive layers 14 and 18 are present so as to provide a continuous conductive plane (for example, VDD and ground planes) with no “holes” in it, and of course the substrate 22 is included so that the substrate is continuous as well.
Therefore, the resulting semi-custom ASIC typically has three types of cells. Functional cells which form circuits that are part of the overall circuit design originally submitted by the designer, spare cells whose function is to provide spare components if they are needed to modify the functionality of the chip after placement & routing at various stages of manufacture, and the filler cells.
One problem with this approach is that the number of cells in a semi-custom ASIC die, and thus the area of the die itself, is typically significantly increased by including the spare cells. For example, in the example given above, the size of the die is effectively increased 10% (from 100,000 cells to 110,000 cells) to accommodate the 10,000 spare cells.
Another problem is that the locations of these pre-connected spare cells may be tied to the locations of other connected spare cells, and thus these spare cells may not be uniformly available over the die.
Another problem is that even when they are not used, these spare cells typically draw quiescent current and thus add to the power consumed by the chip. So the number of spare cells that can be used is limited by the power budget of the chip. And because the locations of these limited number of spare cells may tend to be clustered due to a redundant pattern (for example, the ring oscillator described above), then this may result in areas of the chip lacking a sufficient number of spare cells to fix a defect that may be later discovered.
What is desired, therefore, is a method of effectively utilizing the space that would eventually be filled with filler cells in an integrated circuit in a manner that overcomes the problems associated with the prior art approaches mentioned above, thereby providing an optimum spare cell distribution.